Transconductors in Subthreshold CMOS
نویسندگان
چکیده
| Four schemes for linearizing the transconductance of the basic di erential pair in subthreshold CMOS are examined. They are: source degeneration via (1) diode-connected transistors, (2) a single di usor and (3) symmetric di usors, and (4) multiple asymmetric di erential pairs. We derive equations for the di erential output current for each linearizing technique. We apply a maximally at optimizing criterion to these designs. Finally, we compare each technique in terms of linear range and energetic e ciency.
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